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It doesn't sound like it but they don't have enough detail in the article to say.
It sounds likey they are using a classification model that takes a vectorized text representation of molecules and classifies or scores them by their expected properties/reactivity. They took 39,000 molecules with known reactivity to MRSA to train the model, I assume to classify the structures. Once trained they can feed in arbitrary molecules into the trained model and see which ones are predicted to have antibiotic properties, which they can verify with bench work.
They likely fed in molecules from classes of likely candidate structures, and the model helped focus and direct the wet work.
I'm not up on the latest, but years ago I helped a similar project using FPGAs running statistical models to direct lab work.
I'd be interested to know why FPGAs were selected for this application. I'm not especially familiar with their use cases.
This was years ago before GPU processing really took off, and we wanted the performance, but also, wanted to see if we could develop an affordable discrete lab device that could be placed in labs to aid in computationally directed bench work. So effectively, testing the efficacy of the models and designing ASICs to perform lab tests.
With a CPU or even a GPU, there is a bunch of inefficiencies for every task as they're designed to be able to do pretty much anything - your H265 media decoder isn't going to be doing much when you're keeping a running sum of the number of a certain type of bond in a list of chemicals
With ASICs and a lesser extent FPGAs, you can make it so every single transistor is being used at every moment which makes them wildly efficient for doing a single repetitive task, such as running statistical analysis on a huge dataset. This is because rather than being limited by the multiprocessing ability of the CPU or GPU, you can design the "program" to run with as much multiprocessing ability as is possible based on the program, meaning if you stream one input per clock cycle, after a delay you will get one input per clock cycle out, including your update function so long as it's simple enough (eg moving average, running sum or even just writing to memory)
This is one specific application of FPGAs (static streaming) but it's the one that's relevant here
So it sounds like we're designing the instruction pipeline for maximum parallelism for our task. I was surprised to learn that the first commercial FPGAs were available as early as the '80s. I can see how this would have been an extremely effective option before CUDA became available.
Don't know why they chose them, but I do know they're used in cartridge emulation for older consoles.
Wikipedia says they're great at simulation and parallel processing, which works great here.
https://en.m.wikipedia.org/wiki/Field-programmable_gate_array